1. Technical Field
The invention relates to a field programmable gate array, and more particularly, to a shadow DRAM circuit that is adapted to effect and maintain selected interconnection of various logic and other elements in a field programmable gate array.
2. Description of the Related Art
A field programmable gate array (FPGA) is a programmable integrated circuit logic device that consists of a matrix of configurable logic blocks (CLBs) embedded in a programmable routing mesh. The combined programming of the CLBs and routing network define the function of the device. The device is referred to as an FPGA because the array of CLBs contained on the device can be configured and interconnected by the user in the user's facility by means of special hardware and software.
FPGAs are well known in the art. For example U.S. Pat. No. RE 34,363, reissued on 31 Aug. 1993, describes a configurable logic array that includes a plurality of CLBs interconnected in response to control signals to perform a selected logic function, and in which a memory is used to store the particular data used to configure the CLBs. U.S. Pat. No. 4,642,487, issued on 10 Feb. 1987, teaches a special interconnect circuit for interconnecting CLBs in an FPGA without using the general interconnect structure of the FPGA. U.S. Pat. No. 4,706,216, issued on 10 Nov. 1987, describes a configurable logic circuit that includes a configurable combinational logic element, a configurable storage circuit, and a configurable output select logic circuit. U.S. Pat. No. 4,750,155, issued on 7 Jun. 1988, describes a five transistor memory cell for an FPGA that can be reliably read and written.
Each CLB can provide one or more of the functions provided by an AND gate, flip-flop, latch, inverter, NOR gate, exclusive OR gate, as well as combinations of these functions to form more complex functions. The particular function performed by the CLB is determined by control signals that are applied to the CLB from a control logic circuit. The control logic circuit is formed integrally with, and as part of, the integrated circuit on which the CLB is formed. If desired, control information can be stored and/or generated outside of this integrated circuit and transmitted to the CLB. The actual set of control bits provided to each CLB on the integrated circuit depends upon the functions that the CLB and, more globally, the integrated circuit are to perform.
Each CLB typically has a plurality of input and output pins, and a set of programmable interconnect points (PIPs) for each input and output pin. The general interconnect structure of the FPGA includes a plurality of interconnect segments and a plurality of PIPs, wherein each interconnect segment is connected to one or more other interconnect segments by programing an associated PIP. An FPGA also includes an access PIP that either connects an interconnect segment to an input pin or an output pin of the CLB.
Because the PIPs in the FPGA are programmable, any given output pin of a CLB is connectable to any given input pin of any other desired CLB. Thus, a specific FPGA configuration having a desired function is created by selected generation of control signals to configure the specific function of each CLB in an FPGA, together with selected generation of control signals to configure the various PIPs that interconnect the CLBs within the FPGA.
Each PIP typically includes a single pass transistor (i.e effectively a switch). The state of conduction, i.e. whether the switch is opened or closed, is controlled by application of the control signals discussed above to a transistor control terminal, e.g. a gate. The programmed state of each pass transistor is typically latched by a storage device, such as a static random access memory (SRAM) cell 100, illustrated in FIG. 1. As shown in FIG. 1, a high signal ADDR on address line 102 identifies the SRAM cell to be programmed by turning on an n-type pass transistor 104, thereby allowing the desired memory cell state DATA to be transferred from the data line 101 to a latch 106. The state of the control signal stored in the latch 106 determines whether a pass transistor (PIP) 109 is turned on or off, thereby opening or closing a path in the FPGA interconnect.
An SRAM cell is typically used as a storage device because the SRAM cell reliably maintains its value as long as power is supplied. However, as shown in FIG. 1, because SRAM cell 100 includes two inverters 107/108 and a pass transistor 104, SRAM cell 100 requires significant area on an integrated circuit. Typically, the larger the area needed to implement a PIP, the fewer number of PIPs that can be fit onto an integrated circuit.
In view of the continuing trend to increase the number of complex functions implemented by an FPGA, a need arises for a method to reduce the size of the memory cells used to hold the program for the FPGA interconnect, thereby reducing the size of the FPGA and lowering its cost. Further, smaller memory cells would permit larger capacity FPGAs to be built than were previously possible.
A dynamic random access memory (DRAM) cell, which is much smaller than an SRAM cell, has previously not been used in FPGAs for a number of reasons, including:
1. A DRAM cell is volatile and subject to alpha particle upsets that can change the state stored in the cell; PA1 2. A DRAM must be periodically refreshed. Sensing the DRAM cell, for example to refresh the cell, destroys the current value in the cell; and PA1 3. Nearby signals, or signals running over a DRAM cell, can affect the contents of the cell.